The present invention relates to U.S. Ser. No. 08/948,941 filed on Oct. 10, 1997, now U.S. Pat. No. 6,037,824, claiming the priority based on Japanese Patent Application No. 8-289131 filed on Oct. 13, 1996 and assigned to the assignee of the present application, the whole of the disclosure of which is incorporated herein by reference.
The present invention relates to a digital signal input circuit and a method of testing it, and more particularly to an input interface circuit to which a high-speed and small-amplitude digital signal is applied.
For example, a personal computer includes functional IC blocks such as a CPU, a memory controller and a memory. The memory controller controls an access from the CPU or the other device to the memory. The transfer of data between the CPU and the memory controller and the transfer of data between the memory controller and the memory are performed through buses, respectively.
Data received by each of these or similar IC blocks from the other IC block is in the form of a high-speed and small-amplitude digital signal. Since the amplitude of the signal is too small, the data cannot be handled by a circuit in the IC block as it is. Especially, if an inputted digital signal includes noise superimposed thereon, the determination of a logic level thereof will be difficult. Accordingly, it is common that an input portion of the IC block such as a memory controller or a memory is provided with an input interface circuit which performs discrimination and waveform shaping of an inputted digital signal.
Many conventional input interface circuits includes a combination of a current mirror type differential amplifier and a latch circuit. In this interface circuit, a logical level of an input signal having a small peak-to-peak voltage of, for example, about 0.8 V is discriminated through the comparison thereof with a reference signal by use of the current mirror type differential amplifier, the discriminated input signal is amplified up to a voltage of, for example, about 2.5 V to 3.0 V which can be handled by a digital circuit, and the amplified output signal is held by the latch circuit which is a digital circuit. The test of the operation of such a differential input type input interface circuit includes a test through which the judgement is made of whether or not a set-up operation from a point of time of stabilization of an output of the differential amplifier to a point of time when it can be held by the latch circuit falls within a specified set-up time.
The judgement is made on the basis of two criteria. One is concerned with the timing of the set-up operation, that is, whether or not a transistor in the input interface circuit has a sufficient driving capability for discrimination of a logical level in a prescribed time. The other is concerned with whether or not the sampling for the latch circuit of the input interface circuit is performed in the prescribed time.
For such a test of the operation of the input interface circuit, there has hitherto been used a memory tester which generates an analog signal having a linearly varying rise pattern and applies this analog signal to the input interface circuit in a manner such that the applied analog signal is sequentially shifted by a short time to measure a time until a normal operation is no longer available.
However, the conventional tester provided with the above-mentioned function of generating an analog signal capable of short-time shifts has a complicated circuit structure and is therefore high in cost. Accordingly, an input interface circuit completed through a test using such a costly tester becomes expensive.
Further, JP-A-8-63268(laid open on Mar. 8, 1996) has disclosed an input/output interface circuit provided with an integrating circuit. However, no reference is made to the test of that circuit.
One object of the present invention is to provide an input interface circuit having a function for facilitating a test.
The input interface circuit according to the present invention may be used with the above-mentioned digital IC block.
Another object of the present invention is to provide a method of testing an input interface circuit.
According to one aspect of the present invention, an input interface circuit is provided with an input transistor for receiving a digital input signal, a circuit for generating a reference value, and an integrating capacitor connected in series to a pair of current conducting electrodes of the input transistor for integrating the input signal, a logical level of the input signal being discriminated by comparing an integration of the input signal with the reference value. For a testing function mode, a test transistor is connected to a junction between the pair of current conducting electrodes of the input transistor and the integrating capacitor so that a current driving capability is determined. Also, a discharge path circuit for controllably discharging the integrating capacitor is connected to the junction between the input transistor and the integrating capacitor.
According to another aspect of the present invention, a method of testing an input interface circuit provided with an input transistor for receiving a digital input signal, a circuit for generating a reference value, an integrating capacitor connected in series to a pair of current conducting electrodes of the input transistor for integrating the input signal, a test transistor connected to a junction between the pair of current conducting electrodes of the input transistor and the integrating capacitor, and a discharge path circuit for controllably discharging the integrating capacitor is connected to the junction between the input transistor and the integrating capacitor, includes the steps of:
operating one of the input and test transistors so that fixed current flows through a pair of current conducting electrodes of the one transistor;
operating the other transistor by applying a sequentially varying signal to the other transistor so that current flowing through a pair of current conducting electrodes of the other transistor is sequentially varied;
comparing an output of the integrating capacitor with the reference value to determine a logical level of the input signal, and;
finding a value of the sequentially varying signal when the determined logical level is changed from one state to another.